In general, nonvolatile memory devices of the metal-insulator-semiconductor (MIS) type can be broadly divided into two basic types of devices: Metal Nitride Oxide Semiconductor (MNOS) type transistors and floating gate (FG) type transistors.
MNOS type transistors typically store a charge, which can represent information, within one or more insulating films of a gate insulating film. For example, in the case of a two-layer gate insulating film, charge may be stored at interface states, or the like, formed at a boundary layer between two insulating films. One example of such an arrangement can be an MNOS type device. In addition to such a two-layer arrangement, other types of MNOS type devices can include a silicon oxide film formed on a silicon nitride film. Such devices can be referred to as Metal Oxide Nitride Oxide Semiconductor (MONOS) type devices.
In the case of FG type transistors, charge can be stored in a floating gate which is provided in addition to another (e.g., control gate) of the transistor. For example, a FG type transistor may include a first gate electrode that may be insulated from other conductive structures (e.g., can float) and can be formed on a silicon oxide film. The silicon oxide film may be formed on a main surface of a silicon substrate. An interlayer insulating film, which may include a combination of a silicon oxide film and a silicon nitride film, is formed on the first gate electrode. A second gate electrode, which may be a control gate electrode, is formed on the interlayer insulating film. Such a second gate electrode can cover the first gate electrode.
Write and erasure operations in such nonvolatile storage elements can occur in the following fashion. In an MNOS type transistor, in a write operation, electrons can be injected from the semiconductor substrate into the above-mentioned interface states by direct tunneling. Tunneling can occur through a silicon oxide film with a thickness in the order of 2 nanometers (nm). Conversely, erasure can occur when an electron is emitted from the interface states to the semiconductor substrate. Thus, interface states can become an electron trapping center.
In contrast to the MNOS type transistor, in the case of a FG type transistor write operation, charge can be injected from the semiconductor substrate into a first (i.e., floating) gate electrode. Such a mechanism can be by hot electron injection, with “hot” electrons being generated in the channel region and injected through a silicon oxide film with a thickness in the order of 10 nm. Erasure in a FG type transistor can include emitting electrons from the first gate electrode to the source or channel of the transistor. According to typical conventions, a write state (e.g., charge injected) can correspond to a logic 1 being the stored information. Conversely, an erase state (e.g., charge emitted) can correspond to a logic 0 being the stored information.
In nonvolatile memory devices, referred to as “flash” memories, the above M(O)NOS type transistors or FG type transistors can be utilized as the basic nonvolatile memory element. However, current mass produced flash memory products appear to use only FG type transistors as the nonvolatile memory element.
As the capacity of the above-described flash memory devices increases, it is desirable to continue shrinking the size of nonvolatile memory device elements. In addition or alternatively, it is also desirable to reduce the operating voltages for write, erase and/or read operations in such devices. However, such reductions in size and/or operation voltage can work against the goal of increasing operating speed.
In a FG gate type transistor, a holding characteristic for the information charge can suffer if an insulating film surrounding a floating gate is not sufficiently thick. As a result, a relatively thick tunneling oxide of about 9 nm or more is employed between the main surface of a semiconductor substrate and a floating gate electrode. However, such a tunneling oxide thickness can require a certain operating erasure potential to ensure adequate charge transfer in a write or erase operation. Thus, such a tunnel oxide thickness can limit the extent to which write and/or erase voltages can be reduced.
In addition, the manufacturing processes for FG type flash memory products can be complex and hence difficult to simplify. Thus, as FG type nonvolatile elements are reduced in size, yields can be reduced. Because of this, it can be difficult to reduce the cost of manufacturing such flash memory products.
In contrast to FG type transistors, in MNOS type transistors, a tunnel oxide between the main surface of a semiconductor substrate and a silicon nitride film can be about 3 nm or less. Such a smaller thickness can allow for lower operating voltages. In particular, a smaller write or erase voltage can be used.
Thus, because MNOS type devices present the above theoretical advantage of lower write and/or erase voltages, various studies in recent years have been conducted to make the use of MNOS type devices practical for use in semiconductor integrated circuit devices.
Among various conventional techniques that utilize an MONOS type transistor as a flash memory nonvolatile element is that shown in U.S. Pat. No. 5,768,192 (hereinafter referred to as the first conventional example) and that shown in “Twin MONOS Cell with Dual Control Gates”, 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123, by Yutaka Hayashi et al. (referred to herein as the second conventional example).
The first conventional example will now be described as prior art with reference to FIGS. 24-26. FIG. 24 is a substantially sectional view of a MONOS type transistor proposed as a nonvolatile memory element for a flash memory.
As shown in FIG. 24, a first diffusion layer 102 and a second diffusion layer 103 are formed in a silicon substrate 101. First and second diffusion layers (102 and 103) may be N+ diffusion layers in a main surface of a P-conductivity type silicon substrate 101. A first silicon oxide film 104, a silicon nitride film 105, and a second silicon oxide film 106 can be formed on a silicon substrate 101. Such layers may result in a laminated film (ONO structure) disposed between first and second diffusion layers (102 and 103). Further, a gate electrode 107 is formed using polycrystalline silicon on the second oxide film 106. Such an arrangement can form a fundamental MONOS type transistor.
Next, the basic operation of the above-mentioned MONOS type transistor will be described. In a write operation, charge (electrons in the current example) can be trapped in a silicon nitride film 105. As shown in FIG. 25, a silicon substrate 101 and a first diffusion layer 102 can be kept at a ground potential, a second diffusion layer 103 is set to voltage VW, which can be 5 volts, and a gate electrode 107 can be set to a voltage VGW, which can be on the order of 4 volts. When such voltages are applied, an electron flow 108 (e.g., a channel current) is produced from the first diffusion layer 102, which serves as a source, to the second diffusion layer 103, which serves as the drain. Such a current includes channel hot electrons (CHEs) in the vicinity of the second diffusion layer 103. Such CHEs can cross the barrier of the first oxide film 104 and become trapped in a region of the silicon nitride film 106. This is shown as charge trapping region 109 in FIG. 25. Thus, in the conventional write operation described, information charge can be stored in the region of the silicon nitride film 105 which is located near the end of the second diffusion layer 103.
FIG. 26 shows a read operation of the first conventional example. In a read operation, the second diffusion layer 103, which can serve as a source, is kept at a ground potential, while a first diffusion layer 102, which can serve as a drain, is kept at a voltage VR, which can be set to 3 volts. A gate electrode 107 can be set to a voltage VGR, which can be in the order of 1.5 volts. A silicon substrate 101 can be at a ground potential.
A conventional read operation can vary according to the type of data stored. In the case of a logic “1”, in which electrons are written into a trapping region 109, essentially no current flows between a first diffusion layer 102 and a second diffusion layer 103. In contrast, the case of a logic “0”, in which electrons are essentially not written into a trapping region 109, a current flows between a first diffusion layer 102 and a second diffusion layer 103. In this way, it is possible to read out information written into a conventional SONOS type device.
Referring back to FIG. 25, an erase operation for the first conventional example will now be described. In an erase operation, the silicon substrate 101 and the first diffusion layer 102 are kept and a ground potential, while a second diffusion layer 103 is kept at a voltage VE, which can be set to 5 volts. The gate electrode 107 can be set to a voltage VGE, which can be in the order of −5 volts. When such voltages are applied, energy band bending can occur in a region located at an end portion of the second diffusion layer 103 overlapped by the gate electrode 107. Such band bending can enable “holes”, produced by interband tunneling, to be injected into the trapping region 109 to erase the electron charge therein.
Next, the second conventional example will be described as prior art with reference to FIG. 27. FIG. 27 is a substantially sectional view of a MONOS type transistors proposed as a nonvolatile memory element for a flash memory. A feature of this particular conventional example is how a word line and control gate electrodes (which can become word lines in an array) are formed in a cell array structure.
As shown in FIG. 27, a first diffusion layer 202 and a second diffusion layer 203 are formed in a silicon substrate 201. First and second diffusion layers (202 and 203) may be N+ diffusion layers in a main surface of a P-conductivity type silicon substrate 201. Then, a first control gate electrode 204, second control gate electrode 205, and a word electrode 206 are formed over the silicon substrate 201, between the first and second diffusion layers (202 and 203), and separated by insulating films, as shown.
In FIG. 27, the insulating film between the (first and second) control gate electrodes (204 and 205) and the silicon substrate 201 is an insulating film having an ONO structure, as in the case of the first conventional example. The insulating film between the word electrode 206 and the substrate is single layer silicon oxide film. Further, the insulating film separating (first and second) control gate electrodes (204 and 205) and the word electrode 206 is an insulating film having an ONO structure.
Referring still to FIG. 27, in a write operation of the second conventional example, charge (in this case electrons) are trapped in trapping regions 207 and 208 which are located under the above-mentioned first and second control gate electrodes (204 and 205), respectively. As noted above, trapping regions 207 and 208 can have an ONO structure. In an erase operation, voltages are applied between the first and second control gate electrodes (204 and 205) and first and second diffusion layers (202 and 203), so that holes produced by interband tunneling (as described in the first conventional example) are injected into the trapping regions 207 and 208.
The above first and second conventional examples may have drawbacks.
In the case of the first conventional example, information retention requirements may limit how thin an insulating layer can be between a control gate electrode 107 and a silicon substrate 101. That is, information (e.g., charge) retention requirements may limit how thin a first silicon oxide film 104, a silicon nitride film 105, and a second silicon oxide film 106 can be. The present inventor has conducted various trial experiments on fundamental characteristics of the MONOS structure, like that of the first conventional example. Such experiments having shown that in order to essentially ensure an information retention period of 10 years, for an ONO structure that includes silicon oxide film, a lower limit to a thin film thickness is on the order of 8 nm.
Such a minimum thickness can result in drawbacks. It is desirable to provide as fast an operation as possible in a nonvolatile memory device. Limits in minimum thickness of an insulating film (or films) can result corresponding limits in the read speed of such devices. For example, capacitance per unit area of gate dielectric may depend on overall dielectric thickness/material between a control gate electrode 107 and a silicon substrate 101.
In the above-described second conventional example, a MONOS type transistor has first and second control gate electrodes as well as a word electrode formed in a single memory cell. In particular, control gate electrodes can be sidewall conductive films formed on side walls of the word electrode. When such a structure is used, a size of a control gate electrode in a channel direction can be reduced. This can reduce the effective channel length of the resulting transistor device. In this way, it can be possible to speed up a read operation for the above device.
However, as indicated above, in the second conventional example control gate electrodes are formed on the sides of a word electrode. Thus, control gates electrode lines and word electrode lines (e.g., word lines) are arranged in the same direction within a cell array. Further, in the second conventional example control gate electrode lines and word electrode lines are parallel to bit lines, which are formed by first (or second) diffusion layers. However, due to a common arrangement of circuits peripheral to a memory cell array, it may be desirable to have bit lines in a direction that is perpendicular to word lines. Such an arrangement can be difficult to achieve with the second conventional example.
Also, because a second conventional example has control gate electrodes as sidewall conductive films on a word electrode, control gate electrodes may have very small widths with respect to other wirings. Such small widths can present an increased wiring resistance that introduces delay into signal transmission. In view of this, it can be difficult to incorporate such an approach into memory cell array applications.
In light of the above-mentioned drawbacks of the conventional examples, it would be desirable to arrive at some way of increasing the capacity of a flash memory while reducing the operating voltage and/or increasing the operating speed.
In addition or alternatively, it would be desirable to arrive at a practical way of using a MONOS type transistor as a nonvolatile memory element for a flash memory.